The present invention relates to a method and/or architecture for a random access memory device generally and, more particularly, to a synchronous random access memory device having a burst transfer capability.
Certain microprocessors and memory devices are designed to transfer data using a burst type transfer. The burst type transfer causes the data to be transferred at multiple consecutive addresses without having to present all addresses to the memory device. The burst type transfers may be use a linear sequence where the data at consecutive addresses ate serially transferred. The burst type transfers may use an interleaved sequence where the data at interleaved addresses are serially transferred.
The present invention concerns a device comprising a memory array and a burst sequence generator. The memory array may be configured to store data. The burst sequence generator may be configured to generate a burst sequence in response to address information received by the device. The burst sequence may be configured to identify a plurality of locations for storing data in the memory array. The device may have a maximum operating current of 50 milliamps and/or a maximum standby current of about 25 microamps.
The objects, features and advantages of the present invention include providing a synchronous burst random access memory that may (i) operate in a linear burst sequence, (ii) operate in an interleaved burst sequence, (iii) support single read accesses, (iv) support single write accesses, (v) consume extremely low power, and/or (vi) interface with a memory controller with minimal glue logic.